As opposed to planar complementary metal-oxide-semiconductor (CMOS) devices, vertical transport field effect transistor (VTFET) devices are oriented with a vertical fin channel disposed on a bottom source/drain and a top source/drain disposed on the fin channel. VTFETs are being pursued as a viable CMOS architecture beyond the 7 nanometer (nm) node and beyond.
Combinations of work function metals can be used to achieve various threshold voltages (Vt) in CMOS devices. In a VTFET integration process flow, gate dielectric and work function metals are recessed to a certain level to define the channel length. However, due to the isotropic wet etch characteristics, the outer work function metal is inevitably over-etched (based on a longer exposure time to the wet chemistry), resulting in non-uniform work function metal thickness along the channel. This non-uniformity undesirably causes severe Vt variation from the top to the bottom of the channel.
Therefore, VTFET fabrication techniques that address this problem to improve the uniformity of work function metal thickness along the channel would be desirable.